FET Gate Protection Diode with Asymmetric, Dual Polarity Voltage Capability
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Feb-09
This article describes a process for fabricating an FET gate protection diode with asymmetric dual polarity voltage capability. Such a device can be used in an electrically erasable/programmable read only memory or a non volatile random access memory where a gate potential that is more negative than the substrate potential is required. The disclosed process requires the addition of one mask and two ion-implant steps to an N-MOS FET process.