Very Dense One Device FET Memory Cell
Original Publication Date: 1982-Jul-01
Included in the Prior Art Database: 2005-Feb-09
A processing method is described which leads to very dense one-device FET memory cells having the following main features: Polysilicon-gate FET with conventional micron/submicron deep source diffusion on one side of the gate and several microns deep drain diffusion on the other side of the gate. Source and drain are self-aligned with respect to the gate, the deep drain having alignment-independent dimensions at the same time.