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Fig. 1 shows the improved push-pull driver which includes devices 5, 6, 7, 8 and 9. Devices 5 and 7 are depletion-mode devices, and devices 6, 8 and 9 are enhancement-mode FET devices.
English (United States)
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Push Pull Driver
Fig. 1 shows the improved push-pull driver which includes devices 5, 6, 7, 8
and 9. Devices 5 and 7 are depletion-mode devices, and devices 6, 8 and 9 are
enhancement-mode FET devices.
Devices 5, 6, 7 and 8 are connected as in a conventional depletion mode
load push-pull FET driver. Fig. 2 illustrates the waveform A for the gate input to
the enhancement mode devices 6 and 8. The waveform B represents the output
voltage at the drain of the enhancement mode device 8 for the conventional
depletion load push pull driver of devices 5, 6, 7 and 8.
The invention involves the addition of the enhancement-mode FET device 9
connected with its gate to the output node of the first inverter comprising devices
5 and 6, its source connected to the output or drain electrode of the device 8, and
its drain connected to the VDD potential. The addition of the enhancement-mode
device 9 reduces the rise time, is illustrated b, the waveform C in Fig. 2. For the
conventional push pull driver, for a given combination of width to length ratios for
the devices 5, 6, 7 and 8, a rise time of 5 nanoseconds would be provided at e 0.5 pF output capacitance and a rise time of 10 nanoseconds would be provided
at an output capacitance of 2.5 pF. The improvement in rise time for the circuit
when the enhancement-mode device 9 is added is a 3.75 nanosecond rise time
at a 0.5 pF output capacitance and a 7-nanosecond rise time at a 2.5 pF output