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This circuit will generate a synchronizing pulse to gate the signal lines at a specific time, thus eliminating the need for padding to meet short path criteria and thereby prevent race conditions.
English (United States)
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Jitter Free Synchronizing Pulse
This circuit will generate a synchronizing pulse to gate the signal lines at a
specific time, thus eliminating the need for padding to meet short path criteria
and thereby prevent race conditions.
The circuit is shown in Fig. 1. The shift register latch (SRL) denoted by
TOCGLE-A changes state every cycle. TOGGLE-B is TOGGLE-A delayed by 1
cycle. The outputs of the 2 SRL's are delayed and fed to the combinatorial logic
to create the pulse. The timing diagram is shown in Fig. 2. The + Trigger Clock
(+C) is enveloped within the Trigger Clock (C). Since +C launches + Data (on
pin 21 of the SRL) and C launches - Data, the output of the SRL is not
symmetrical (i.e., the output of TOGGLE-A shrinks by SWl in 1 cycle and
expands by SW1 in the next cycle).
TOGGLE-B has the same characteristic as TOGGLE-A except that it is
delayed 1 cycle. The synchronization pulse is created by combining signals that
are launched by the same clock (-C in this case). The time that the leading edge
of the pulse occurs is determined by the delay block; thus this time can be
preprogrammed to fit a particular application.
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