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Vertical JFET Integrated with Self Aligned Bipolar Process

IP.com Disclosure Number: IPCOM000049894D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Gaur, SP Malaviya, SD Srinivasan, GR [+details]

Abstract

An N channel JFET (junction field-effect transistor) is described using bipolar technologies. The JFET device has low threshold voltage with tight tolerance. The device may be implemented in enhancement or depletion form by threshold adjustment. The process provides very tight control of the channel length. Also, there is no extra masking or process step, if a Poly resistor or a specific resistivity is required.