Browse Prior Art Database

JFET Structure

IP.com Disclosure Number: IPCOM000049896D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Anantha, NG Bhatia, HS Bhatia, SS [+details]

Abstract

An oxide sidewall, reactive ion etching technique is used to fabricate a double-gated junction field-effect transistor (JFET).