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Parity Checked Decoder

IP.com Disclosure Number: IPCOM000049910D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Bunse, P Getzlaff, KJ Hajdu, J Richter, S [+details]

Abstract

Fig. 1 shows an arrangement for decoding an 8-bit operation code into one out of 256 output lines. Between operation register 1 and decoder 6 a predecoder is located for decoding the upper four bits 0 to 4 (group A) into one out of 16 signals A0 to AF and for decoding the four lower bits 4 to 7 (group B) into one out of 16 signals BO to BF. The predecoder receives true and complementary OP code signals generated by means of inverters 2. Each of a series of AND gates 3 combines four bits for the sixteen output signals. Inverters 4 are used as buffers, and inverters 5 serve to generate intermediate output signals.