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Exclusive NOR Circuit

IP.com Disclosure Number: IPCOM000049920D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Bansal, J [+details]

Abstract

A high speed exclusive NOR circuit is shown in the figure, embodied in CMOS field-effect transistor technology. Devices P1 and P2 are enhancement mode P channel FET devices, and devices N1 and N2 are enhancement mode N channel FET devices. The source of device N1 is the logical input A, which is also connected to the gates of the devices P2 and N2. The source of the device N2 is the logical input B, which is also connected to the gates of the devices N1 and P1. The sources of the devices P1 and P2 are connected to the positive potential +VDD. The node X is shorted to the node Y and is the logical output of the circuit.