Read Only Memory Slow Zero Change Speed Tester
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
This article describes a checking circuit for electrically alterable or programmable memory chips. The specific type of problem to be checked is that of a slow transition to a zero state on read out. In checking memories, after they are written with data, a slow changing bit cell that is not written with data will have no effect in the acceptability of the device. However, a slow cell for the zero transition may go undetected since a one condition (positive) exists, no speed checking is necessary, and the usual testers may overlook the fact that, indeed, the cell is intended to change to a zero upon writing. The circuit above checks for the serial transition between 400 and 500 nanoseconds after the start of a read-out cycle. This is the time period during which a slow to change zero transition will occur.