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Johnson Counter with Error Correction

IP.com Disclosure Number: IPCOM000049940D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Miller, GD Nicholson, LW [+details]

Abstract

A Johnson (or Mobius) counter 10 (Fig. 1) provides a simple way for obtaining n clock phases for a digital system, by means of a simple two way decode on a feedback shift register having n/2 flip-flop stages 11 and driven by a high-speed clock 12. Random noise can cause a spurious sequence to be locked into stages 11, thus producing incorrect phase outputs Q1-Q4. Such sequences can be corrected by an additional stage 13 which provides a (redundant) reset QR to all stages 11, to clear out any extraneous bits set by a noise pulse. Regardless of the initial states of stages 11, eventually a one-zero transition will propagate through counter 10, activating reset QR. Thereafter, QR is redundant, until an incorrect sequence occurs. Fig.