Method for Reimplementing a Faster Design Utilizing Dynamic Partitioning
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
In the design of logic circuits, it is frequently desired to redo the design in another technology, to obtain a faster design, involving fewer levels, to obtain a more economical design in terms of the number of circuits, or to transform the description of the design into a higher level language. Two algorithms [1,2], embodied in PL/I programs P* and R*, serve to perform these functions; the high-level languages are PL/R and BDL/CS. These programs have a problem inherent in them: for large designs the required storage and running time become excessive.