Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
This article describes a MOSFET structure with minimal parasitics for high performance application. It is also suitable for implementing latch-up free CMOS (complementary MOS) circuits. Fig. 1 shows a cross-sectional view of the new MOSFET structure. A major feature of this structure is that it has buried polysilicon regions 2,3 insulated, for example, by silicon dioxide regions which are disposed over and under regions 2,3.