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Self Aligned Gate Process Using Pattern Transfer for High Speed MESFET Fabrication Disclosure Number: IPCOM000049996D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09

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Ephrath, LM Fang, FF Isaac, RD Seitz, HK [+details]


A method is described to decrease the parasitic source to gate and gate to drain resistance in MESFET devices/ The benefit of the reduction is increased switching speed and reduction of dissipated power. The reduction is achieved in a self aligned process by extending the high conductivity ion implanted regions of the source and drain very close to the gate. The individual process steps are shown in Fig. 1. The key is to form a temporary gate-like structure on thin SiO(2) from poly-Si as shown in Fig. 1A. The sidewalls of this structure are tapered. This pattern is then used as an N+ I/I mask for source and drain areas. The size of these areas is determined by the recessed oxide isolation (ROX) pattern.