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Regular Iterative Testing Disclosure Number: IPCOM000050025D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09

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Roth, JP [+details]


The testing of cyclic (sequential) circuits for failure is of fundamental importance to very large-scale integration (VLSI) computers. Level sensitive scan design (LSSD) is a method of adding hardware, about 20 percent, which converts cyclic testing to acyclic, enormously simplifying testing. Others have proposed an iterative method of test generation having the disadvantage that it could not be guaranteed that the tests generated were of indeterminacies. On the other hand Roth introduced the method of REGULAR design which, for a certain cost, guaranteed determinate operation in regular networks.