Browse Prior Art Database

Cache Organization with Various Line Sizes

IP.com Disclosure Number: IPCOM000050033D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09

Publishing Venue

IBM

Related People

Authors:
Tan, KG [+details]

Abstract

From simulation data, it is well known that for a given size and organization of CPU cache, the buffer miss ratio (BMR) decreases as the line size increases. It is also known in a given cache organization that instruction references have lower BMRs than data references. Since instructions are of a "read-only " nature, it is advantageous to keep the line size long. The data references are subject to change, and are shared among processors in a MP (multiprocessor) environment. Therefore, it is better to make the data line size small for MP considerations. This article describes a central cache organization which provides long lines for instructions and short lines for data references (Fig. 1).