Cache Miss Director - A Means of Prefetching Cache Missed Lines
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-09
In a computing system with a cache, when the CPU encounters a storage reference that cannot be satisfied by the cache (a demand miss), processing usually must be delayed for an access to main storage. Because of the increasing disparity between CPU and main storage speeds, the penalty for cache misses is both substantial and increasing in cycles per instruction. Therefore, one needs to forestall "demand misses" by guessing what lines will be needed in the cache.