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Use of Memory Cache for Main Memory Failure Mode Analysis

IP.com Disclosure Number: IPCOM000050087D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Kerchmar, K Mehal, VJ Tibbett, OM [+details]

Abstract

The greatest advantage of FET random-access memory (RAM) chips is their density. However, their worst disadvantage is that of reliability. The reliability of RAM memory is measured by the number of the SBEs (single bit errors) per address of ECC (error correction code) block of data. This means that ECC allows one SBE per address of a minimum memory readable data block which can be four, eight, sixteen, etc., bytes of data depending on processor memory bus size and equivalent ECC design. Further, the field performance of FET RAMs is relatively poor whenever two SBEs are 'lined up' within the same ECC address. This creates DBE (double bit error) or MBE (multiple bit error), which can not be ECC error corrected. DBE or MBE requires array card(s) replacement.