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Process to Improve Reliability and Performance of Double Polysilicon Gate Device

IP.com Disclosure Number: IPCOM000050127D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Aboelfotoh, MO Tsang, YL [+details]

Abstract

In a process for making an FET device having two polysilicon gates, the first polysilicon layer 20 is deposited following first gate 16 enhancement or depletion implant to form an N-channel 14 in a P-type substrate 10, as shown in Fig. 1. A layer of silicon dioxide 22 is then deposited over the first polysilicon layer, and is followed by the patterning of the first polysilicon layer using a dry etching technique such as reactive ion etching. The second gate oxide layer 18 is then regrown after the removal of the first gate oxide layer. The interpoly oxide layer 24 (the silicon dioxide layer between the first and second polysilicon layers 20 and 26) is normally grown at the same time as the second gate oxide layer 18.