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Structured Macro Disclosure Number: IPCOM000050153D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10

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Stoops, EH [+details]


Existing integrated circuit chip images typically have three vertical power bus pairs located on the left and right sides and up the middle of the chip. One problem with this chip image is that horizontal wiring channels are readily blocked after the placement of a logic macro on the chip.