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Traps for Mainline Microcode Function

IP.com Disclosure Number: IPCOM000050173D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Lemaire, CA [+details]

Abstract

The performance of microcode for fetching operands and interpreting higher level instructions can be improved by testing certain conditions in the Central Processing Unit (CPU) and taking a trap to a special microcode routine if an operand spans certain address spaces. The microcode trapping apparatus provides the hard branch to specific control storage addresses upon detection of microcode specified conditions which result from CPU operations. If the condition specified is not detected, the microcode continues executing instructions determined by the normal next address arrangement. If the condition specified is detected, the microcode traps to the address reserved for that condition's trap, execute the microcode to handle that condition, and return to the path which would have been taken had no trap occurred.