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Controlling Selective Resets Disclosure Number: IPCOM000050196D
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10

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Huntley, JD Saavedra, F Scott, EK [+details]


A pair of processors share a volatile cache and a plurality of retentive data storage devices. Upon receiving a selective reset from a controlling unit such as a host, use of a shared memory cache is inhibited. Detection of an error in either of the processors also results in executing a selective reset which is internally initiated. A flag is set prior to initiating the internal selected reset. Upon completion of the selected reset, the flag is sensed. If the flag is set, caching is permitted; otherwise, caching is prohibited.