Efficient Handling Of Load Multiple Instruction
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
A method is described herein for minimizing the delay due to address generation interlocks (AGIs) caused by the LOAD MULTIPLE (LM) instruction in high performance pipelined machines. First, some characteristics of interlocks caused by LM are described. Then, ways of minimizing these delays, based on these characteristics, are described. Parts of these mechanisms are applicable to current high performance machines like the IBM 3033.