High Speed Cycle Steal Technique for IBM Series/1 I/O Channel
Original Publication Date: 1982-Sep-01
Included in the Prior Art Database: 2005-Feb-10
A technique is described for increasing the input/output (I/O) data transfer rates for the IBM Series/1 processor. This technique enhances the existing Series/1 I/O architecture such that the existing device compatibility is maintained while enabling the design of new I/O devices that can make use of the added high-speed cycle-steal capability.