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Self Aligned Deep Trench Isolation for Bipolar Transistors

IP.com Disclosure Number: IPCOM000050298D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Malaviya, SD [+details]

Abstract

A deep trench is formed in silicon by using a thin stud opening as the mask. The width can be less than a micron. The active area is protected by a thin silicon dioxide, silicon nitride composite layer, while the rest of the area is etched for recessed oxide isolation (ROI). A thin layer of chemical vapor deposited (CVD) polysilicon may be formed before the oxidation step in order to minimize the "bird's beak" structure. The trench is oxidized simultaneously with the formation of the ROI.