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There has always been a need for better electrical modeling of lateral PNP transistors, but recently, with the development of high density random-access memories, this need has become more acute.
English (United States)
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Electrical Model Improvement of Lateral PNP Isolated Transistor
There has always been a need for better electrical modeling of lateral PNP
transistors, but recently, with the development of high density random-access
memories, this need has become more acute.
Certainly, the use of lateral PNPs in integrated bipolar circuits (memories,
MTL circuits, etc.) has suffered from this deficiency, and limited the number of
possible applications. The present model improves the known ones, especially
concerning its tolerance to geometrical variations (e.g., mask misregistrations),
and statistical processing resulting therefrom. The point deemed new in the
present model is related to the modeling of the current injected into the substrate
in both direct and indirect mode operations. This current is considered to be the
sum of the collector currents of three parasitic transistors modeled separately.
It is known that the need for increased circuit densities leads designers to use
tighter design ground rules to build their devices. One result is to reduce the
space between isolation diffusion and the emitter (or collector) diffusion of the
lateral PNP transistor (P+ emitter, N epitaxy, N+ base, P+ collector). In fact, the
state of the art in silicon technology allows the use of isolation spacings that are
of the same order of magnitude as the distance between the emitter and collector
diffusions. In other words, this means that the physical base width of the
parasitic transistor (P+ emitter, N epitaxy, N+ base, P+ isolation) is as small as
the regular lateral transistor. This can be seen in Fig. 1.
Also, in case of misalignment the base width of the parasitic transistor could
be less than the base of the regular transistor. Then the emitter of a stripe-
shaped transistor (the most widely used geometry) will inject current (IE) towards
the isolation walls over three sides, collector current. When this situation occurs,
the apparent external and the resulting substrate current (IX) will be greater than
the lateral current gai...