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Generation of Fault Oriented Test Sequence

IP.com Disclosure Number: IPCOM000050354D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Brown, A Cheng, DD Koo, CC Ofek, H [+details]

Abstract

The generation of a fault oriented test sequence for a sequential circuit is shown in the figures. It is accomplished by successfully generating three components: Homing Sequence, Test Condition, and Drive-Out Sequence. The Generation of the Fault-Oriented Test Sequence (GEFTS) algorithm takes as imput, the block (Boolean) level description of the logic, and a specification of the fault in the logic. The input is transformed to a high level model- the Logic Flowgraph (LFG). This particular flowgraph is called the "Good Machine LFG" (GMLFG). The description of the fault is used to modify the GMLFG by reflecting the existence of a constant level logical value at the pin associated with the fault. The modified model is the "Bad Machine LFG" (BMLFG).