Browse Prior Art Database

Chip Attachment Structure for High Performance, Efficiently Cooled Semiconductor Chip Carriers

IP.com Disclosure Number: IPCOM000050401D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Ho, CW Shapiro, EE [+details]

Abstract

One chip to package joining approach is the flip-chip C-4 solder ball joint. This approach has unique advantages and disadvantages. The advantages are: capability for batch fabrication, high I/O pin count due to area array and small pin size, good reliability, and low pin inductance and capacitance. The notable disadvantages are the difficulty with which heat is removed from the back side of the chip and the potential damage to the rigid lead tin C-4 solder balls arising from lateral stresses created by different thermal expansion rates in the chip and substrate materials. Future VLSI (very large scale integration) high performance semiconductor chips will require increased power dissipation, increased pin count, smaller pin grids and, therefore, smaller pins.