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Reduction of Punchthrough in Josephson Latching Logic Disclosure Number: IPCOM000050413D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10

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Anderson, CJ [+details]


In Josephson latching logic circuits, the phenomenon of punchthrough can occur when a logic element fails to reset to its zero voltage state during the transition of the power supply through zero. A technique for reducing the probability of punchthrough is described where the power supply regulator is biased in its resonances.