Browse Prior Art Database

Reduction of Punchthrough in Josephson Latching Logic

IP.com Disclosure Number: IPCOM000050413D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Anderson, CJ [+details]

Abstract

In Josephson latching logic circuits, the phenomenon of punchthrough can occur when a logic element fails to reset to its zero voltage state during the transition of the power supply through zero. A technique for reducing the probability of punchthrough is described where the power supply regulator is biased in its resonances.