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Reduced Diffusion Capacitance in Logic Macros with Droppable Inputs

IP.com Disclosure Number: IPCOM000050496D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10

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Related People

Burke, RD Kouba, DJ [+details]


An FET circuit design structure is disclosed which enables the circuit designer to reduce the diffusion capacitance in logic macros which have droppable inputs.