Timing Analysis Model with Micro Block
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Timing Analysis (TA) runs are preceded by steps in which all hardware logic is reduced to micro circuit blocks with delays. The following describes a means of marking the blocks with TA flags and the programs for interpreting the flags. These operate in such a way that it is possible to obtain the full TA modeling capability without losing any delay information.