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Timing Analysis Model with Micro Block

IP.com Disclosure Number: IPCOM000050515D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10

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Related People

Cheng, DD Hitchcock, RB Smith, GL [+details]


Timing Analysis (TA) runs are preceded by steps in which all hardware logic is reduced to micro circuit blocks with delays. The following describes a means of marking the blocks with TA flags and the programs for interpreting the flags. These operate in such a way that it is possible to obtain the full TA modeling capability without losing any delay information.