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Increased Valid Data Readout Time in Static RAM

IP.com Disclosure Number: IPCOM000050534D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10

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Lawrence, JA [+details]


Adding a secons, cascaded output latch on each bit line of a static FET (field-effect transistor) read/write RAM (random-access memory) array greatly increases the proportion of the RAM cycle time during which the output data line is valid for reading by external circuits.