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A means is provided for increasing logical capabilities of AND array product terms with optimum layout density and wirability. Furthermore, the AND array logical structure can be dynamically changed.
English (United States)
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Logical Enhancements to FET and Array Structures
A means is provided for increasing logical capabilities of AND array product
terms with optimum layout density and wirability. Furthermore, the AND array
logical structure can be dynamically changed.
In the implementation of LSI (large-scale integration) digital
computer structures (such as microprocessors and high-level language
processors), it is often necessary to add logical power to AND
arrays, henceforth increasing the semantical functions within an AND
array. Such functions are required when implementing high-level
languages with conventional PLA (programmable logic array) circuitry.
The means of implementing the aforementioned enhancements in an AND
array using an FET LSI technology is described. Furthermore, it
allows changing the logical structure of an AND array dynamically
without drastically impacting density or performance when emulating
complex tasks with an optimum number of "logical gates" (or number of
effective logical gates).
Additional logical functions are created within an AND array by manipulating
the appropriate AND array product terms and/or properly gating such terms. For
an AND-OR array configuration, this essentially implies removing logical
functions from the OR array and including them in the AND array with a minimum
physical density impact but a considerable AND array logical density
Although this article deals with means capable of a considerable proliferation
of complex logical functions, the implementa...