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This article concerns a technique for the electrical location of shorts between adjacent column and row lines on a matrix-addressable display, such as an electrochromic display.
English (United States)
This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately
71% of the total text.
Page 1 of 2
Display Array Fault Location
This article concerns a technique for the electrical location of shorts between
adjacent column and row lines on a matrix-addressable display, such as an
The technique will be described in relation to the circuit
shown in Fig. 4 of published European Patent Application 0042893
which is reproduced here modified as necessary for performing the
electrical location of shorts but otherwise using the same reference
numerals. The reader is therefore directed to the above patent
application for an overall description of circuit operation. The
modifications are twofold:
1) A line common to the rows, the power supply line + V, is
split into two lines + V1 and + V2 and consecutive row lines
42 are connected alternately to the two power supply lines
via their respective transistors 45.
2) A line common to the columns, the erase drive line 54, is
split into two lines E1 and E2, and consecutive column lines
43 are connected alternately to the two erase drive lines
via their respective transistors 53.
With these modifications a test for shorts between adjacent row lines is made
by clocking a single '1' through the row shift register 38 while alternately
energizing the two power supply lines + V1 and + V2. A short between adjacent
row lines 42 is indicated by the presence of current on the power supply line not
energized in each clock period.
A test for shorts between adjacent column lines is made by clocking two