The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Oxide Wall Isolation for FET Integrated Circuits

IP.com Disclosure Number: IPCOM000050753D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue


Related People

Hu, GJ Isaac, RD [+details]


This article presents a proposal for a simple and effective isolation structure for FET (field-effect transistor) integrated circuits. This isolation structure is particularly attractive for CMOS (complementary metal oxide Semiconductor). As shom in Fig. 1, The isolation between the n and the p channel devices consists of an oxide wall and a heavily doped region down below. When the doping concentration of this heavily doped region is sufficiently high (over 1 x 10/19/ cm/-3/), the minority carrier life time becomes so short that the parasitic bipolar latch-up problem can be significantly reduced.