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Dual-polarity polycrystalline silicon (poly-Si) gates which are useful in CMOS integrated circuits can be readily fabricated by novel simplified processes described in this publication.
English (United States)
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Methods for Fabricating P/+/ and N/+/ Poly SI Gates in a Single Poly SI
Layer for Mosfet Applications
Dual-polarity polycrystalline silicon (poly-Si) gates which are useful in CMOS
integrated circuits can be readily fabricated by novel simplified processes
described in this publication.
The performance of high-density CMOS integrated circuits utilizing poly-Si
gates is significantly enhanced by the use of p+ poly-Si and n+ poly-Si gates in
the p-channel and n-channel devices, respectively. Compared to single-polarity
gate structures, the fabrication of such dual-polarity devices requires an
additional lithographic masking level which results in increased cost and
processing complexity. Two alternative processes for fabricating dual-gate
structures using the same number of lithographic masking levels as single-
polarity gate devices with a minimal increase in processing complexity will be
The processes are restricted to the fabrication of the p+ and
n+ poly-Si gates. The starting point, shown in Fig. 1A, represents a
typical cross-section of a CMOS structure after ion implantation of
the deep n-type well and p+ field, and growth of the recessed oxide.
Figs. 1A, 1B, 1C and 1D illustrate the steps of Process I, which are
as follows: Step 1 (Fig. 1A)
- Deposit poly-Si (approx. 300 nm).
- Apply resist.
- Define gates.
- RIE 90% poly-Si.
- Strip resist.
(Alternatively, RIE 100 % poly-Si,