Browse Prior Art Database

Multiple I/O Channel Technique

IP.com Disclosure Number: IPCOM000050788D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Bhansali, MM Cannon, JW [+details]

Abstract

Present I/O channel data rates are limited when multiple cycle stealing (CS) devices are interleaved. This limitation is overcome by the addition of two controller lines per channel, identified as poll return and service gate lines. Two channels per card file (full width) or expansion unit can efficiently improve the I/O data rates. This arrangement enhances the poll timing response, which impacts the channel performance significantly. The channel performance is improved by improving through timings shown in the cycle steal service sequence diagram of Fig. 1 and the polling mechanism and timing diagrams of Figs. 2 and 3, respectively.