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Merged Programmable Logic Array Using Two Bit Read Only Storage Device Disclosure Number: IPCOM000050804D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10

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Kotecha, HN [+details]


This programmable logic array (PLA) includes a single read-only storage (ROS) IGFET device to provide programming of information for both AND and OR arrays within a merged array space. The IGFET device has interchangeable source and drain regions and is selectively programmable to exhibit bilateral channel current, unidirectional channel current from source to drain or from drain to source, or no channel current. Programming is achieved by modifying the field in the channel region adjacent to one or both of the source-drain regions such that the effective threshold voltage of the IGFET is raised or not depending upon whether or not the field modification is present at the effective source end of the channel. Field modification at the effective drain region has no effect on the threshold voltage.