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Incorporating an electrostatic discharge (ESD) path into semiconductor modules will reduce their susceptibility to ESD damage due to pin to cap voltages.
English (United States)
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Reducing Electrostatic Discharge Susceptibility in Semiconductor Modules
Incorporating an electrostatic discharge (ESD) path into semiconductor
modules will reduce their susceptibility to ESD damage due to pin to cap
High voltage (>100 V) potential differences with variable charge capacities
occur in normal and even protected handling of semiconductor modules. These
potential differences, when impressed across the semiconductor package, will
discharge through any convenient path. The result, in a significant fraction of the
cases, is destruction of the semiconductor chip. Two of the most common forms
of electrostatic discharge are signal pin to voltage pin (pin to pin) and signal pin
to module cap (pin to cap). It is common to reduce pin to pin ESD sensitivity by
providing a path for ESD potential discharge.
Susceptibility to ESD damage can be further reduced by incorporating an
ESD discharge path for pin to cap ESD potentials that will withstand ESD
discharges of approximately the same potential as the pin to pin case. The
design guideline is to include a deliberate ESD potential relief path between the
metal module cap and the common semiconductor substrate potential. This path
would include an insulating gap long enough to assure that there would be no
direct potential applied to the metal module cap (for safety) and short enough to
present a preferred path for signal pin to cap ESD potential relief. This design
would channel pin to cap ESD discharge...