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Tri-State Driver Control Disclosure Number: IPCOM000051010D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 27K

Publishing Venue


Related People

Norgren, KS: AUTHOR [+1]


A circuit for using the data per se to control its associated tri-state bus driver is described.

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Tri-State Driver Control

A circuit for using the data per se to control its associated tri-state bus driver is described.

The use of tri-state bus drivers is well-known in the art. The third state provides a high output impedance which is neither on nor off; i.e., the voltage corresponds to neither of the other two states. Open collector and similar dot- active devices can thereby be connected directly to the bus. A pull-up resistor is usually used to keep the bus at the "off" voltage. A driver supplying an "on" voltage changes the bus signal, which has a fast rise or fall time because of the high impedance supplied by the remaining bus drivers.

Tri-state bus drivers require bus steering or enabling signals which essentially control the states of drivers so that only one set of signals is on the bus at one time. Efficient use of the bus is reduced by the time delay between disabling one set of drivers and enabling another set of drivers.

The circuit of Fig. 1 eliminates the need for bus steering signals by controlling the tri-state driver with the data itself. In the circuit, a data in "on" state is considered negative. After a delay dt, the negative signal enables the tri-state driver and the latter's output signal is forced low.

When the data-in signal is returned to a high, the driver's output signal returns to a high with a rise use time as shown by the solid line in Fig. 3. After a time delay dt, the tri-state driver is disabled, i.e., returns to the high-ou...