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Bus Speed Adapter Disclosure Number: IPCOM000051110D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10

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Cukier, M Epenoy, G Pilost, D [+details]


This article describes a bus speed adapter which enables a microprocessor with a single high speed bus architecture to be attached to a plurality of low speed I/O devices. The bus speed adapter comprises a pair of random-access memories (RAMs) which behave as a high speed I/O device when seen by the microprocessor and as a low speed microprocessor when seen by the I/O devices.