Browse Prior Art Database

Bus Speed Adapter

IP.com Disclosure Number: IPCOM000051110D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Cukier, M Epenoy, G Pilost, D [+details]

Abstract

This article describes a bus speed adapter which enables a microprocessor with a single high speed bus architecture to be attached to a plurality of low speed I/O devices. The bus speed adapter comprises a pair of random-access memories (RAMs) which behave as a high speed I/O device when seen by the microprocessor and as a low speed microprocessor when seen by the I/O devices.