Browse Prior Art Database

Circuit for Setting an Electronically Alterable FET in an Array for Controlling a Generalized Logic Circuit

IP.com Disclosure Number: IPCOM000051120D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Larsen, TA: AUTHOR

Abstract

An electronically alterable field-effect transistor (FET) has Its drain terminal connected to the source terminals of a second and third FET. The second FET normally has Its drain connected to a potential point so that it acts as a load resistance for the alterable FET. The third FET has Its drain and gate connected In an X-Y selection matrix. During an operation to set the state of the alterable FET, the second FET is isolated from the circuit at its drain terminal. The two control gates of the alterable FET are successively given potential to turn off and then to turn on the alterable FET. During the turn-on step, the third FET is selectively turned on to enable the alterable FET to store charge on its floating gate.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 63% of the total text.

Page 1 of 2

Circuit for Setting an Electronically Alterable FET in an Array for Controlling a Generalized Logic Circuit

An electronically alterable field-effect transistor (FET) has Its drain terminal connected to the source terminals of a second and third FET. The second FET normally has Its drain connected to a potential point so that it acts as a load resistance for the alterable FET. The third FET has Its drain and gate connected In an X-Y selection matrix. During an operation to set the state of the alterable FET, the second FET is isolated from the circuit at its drain terminal. The two control gates of the alterable FET are successively given potential to turn off and then to turn on the alterable FET. During the turn-on step, the third FET is selectively turned on to enable the alterable FET to store charge on its floating gate. An array of these circuits is arranged to control an array of FETs that form switches in a generalized logic circuIt. The circuit reduces the power that is required for normal operation because the second FET Is a lower current device than the third FET.

A generalized logic device has an array of logic gates that are interconnected through switches that are controlled by memory elements. A particular pattern of 1's and O's in the memory elements establishes an interconnection of the logic gates for a particular logic function. Some FETs are constructed with a floating gate that can be given a charge or can be discharged so that the FET remain...