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A test generator is able to separately control the latch (L1) and trigger (L2) clocks in this LSSD (level sensitive scan design) latch set.
English (United States)
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Testable Single Phase Clock
A test generator is able to separately control the latch (L1) and trigger (L2)
clocks in this LSSD (level sensitive scan design) latch set.
The invert circuit (N) 10 is present to provide an overlap of the L1 and L2
system clocks, thus protecting the mid-cycle short path between L1 and L2 (Figs.
1 and 2). Fig. 3 shows input voltage levels for various operating sequences of
the circuit in Fig. 1. As shown in Row I, during system operation all clock inputs
are held positive except the system clock input which receives the system clock
pulse sequence. To test the operation of various functions of the circuit, the input
voltage levels are sequenced between the levels shown in Row A and the row
describing the test. For instance, to test the system clock, the input circuit is
sequenced by placing the input levels shown in Row A followed by the input
levels shown in Row B and returning to the input levels shown in Row A. To test
the scan clock Ll, the input voltage sequence is Row A followed by Row C
followed by Row A, and so on.
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