Browse Prior Art Database

Testable Single Phase Clock

IP.com Disclosure Number: IPCOM000051146D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Jones, SW [+details]

Abstract

A test generator is able to separately control the latch (L1) and trigger (L2) clocks in this LSSD (level sensitive scan design) latch set.