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Dense CMOS Static Random Access Memory Layout

IP.com Disclosure Number: IPCOM000051156D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Hiltebeitel, JA Jasmin, JE [+details]

Abstract

A static random-access memory layout is provided in complementary metal oxide semiconductor (CMOS) technology with minimized cell area by sharing a diffusion well and contacts. This cell layout is similar to, but denser than, the layout of the cell illustrated in the preceding article, the cells being layouts of a known CMOS static random-access memory cell having first and second cross-coupled N channel transistors, third and fourth N channel input/output transistors, first and second P channel load transistors, a pair of bit/sense lines connectable to the cross-coupled transistors through the input/output transistors and a word line connected to the gate electrodes of the input/output transistors.