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Overlapping Address Generate Delay Disclosure Number: IPCOM000051226D
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10

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Pomerene, JH Puzak, TR Rechtschaffen, RN [+details]


The performance of pipelined processors can be enhanced if delays associated with the decoder, such as Address Generate Interlock and Branch Target Fetch, can be overlapped.