The following operators can be used to better focus your queries.
( ) , AND, OR, NOT, W/#
? single char wildcard, not at start
* multi char wildcard, not at start
(Cat? OR feline) AND NOT dog?
Cat? W/5 behavior
(Cat? OR feline) AND traits
Cat AND charact*
This guide provides a more detailed description of the syntax that is supported along with examples.
This search box also supports the look-up of an IP.com Digital Signature (also referred to as Fingerprint); enter the 72-, 48-, or 32-character code to retrieve details of the associated file or submission.
Concept Search - What can I type?
For a concept search, you can enter phrases, sentences, or full paragraphs in English. For example, copy and paste the abstract of a patent application or paragraphs from an article.
Concept search eliminates the need for complex Boolean syntax to inform retrieval. Our Semantic Gist engine uses advanced cognitive semantic analysis to extract the meaning of data. This reduces the chances of missing valuable information, that may result from traditional keyword searching.
The overlap of decoder delay in the categories of Taken Branch and Address Generate Interlock susceptible to Load Bypass is accomplished via the following mechanism.
English (United States)
This text was extracted from a PDF file.
100% of the total text.
Page 1 of 1
Mechanism to Overlap Decoder Delay with Long OPS
The overlap of decoder delay in the categories of Taken Branch and
Address Generate Interlock susceptible to Load Bypass is accomplished via the
Current highly pipelined processors will stop decoding during the processing
of a multi-cycle E-unit operation (LONGOP) since the Instruction Queue will fill or
"ALL OARS (Operand Address Registers) BUSY" will be raised. The decoder
can continue to "process" instructions during these idle cycles in the hope of
finding the "next delay" which it can resolve directly. This delay, such as a
LOAD-induced Address Generate Interlock or a TAKEN BRANCH TARGET
fetch, if unrelated to the LONG OP, can be overlapped with: the intervening
instruction processing, or (if the LONG OPS will allow or will permit an
intervening cache access) with the Long Op itself. The hardware implementation
of this look-ahead to the next delay is reduced by the observation that the
decoder which is used to do this look-ahead is currently unused during the delay.