Exact Interrupt Capability for Processors Using a Packet Switching Storage Channel
Original Publication Date: 1982-Aug-01
Included in the Prior Art Database: 2005-Feb-10
This article describes a technique for providing "exact interrupts" in the address translate or storage protect mode for a high-speed microprocessor which employs pipelining and a packet-switching main storage channel. "Exact interrupt" means that sufficient information concerning the processor state can be saved, the interrupt serviced, and the previous state restored so that the interrupt is invisible to the program that was interrupted.