Browse Prior Art Database

Dynamic First Stage for a Shift Register

IP.com Disclosure Number: IPCOM000051298D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10

Publishing Venue

IBM

Related People

Authors:
Moore, VS Thoma, NG [+details]

Abstract

A dynamic register stage is described that may be used as an L1 latch i a Level Sensitive Scan Design (LSSD) compatible system, such as that described in U. S. Patent 3,783,254, or as a clock stage in any shift register.