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High Throughput Logic Disclosure Number: IPCOM000051333D
Original Publication Date: 1981-Jan-01
Included in the Prior Art Database: 2005-Feb-10

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Rhodes, KE [+details]


A test sequence comprising groups of coherent subsequences is performed rapidly by storing, with each test instruction in the sequence, the address for the next instruction in the sequence if the test is passed and, in addition, the address for an alternate next instruction should the test not be passed. This technique is particularly useful in routines such as the matrix or feature examination of a character image for character recognition, since each instruction contains the information necessary to immediately bypass subsequent tests which become unnecessary due to the passing or failure of any particular test.