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For testing a VLSI (very large-scale integration) semiconductor chip with logic circuits and a storage embedded therein, the logic circuits and the storage must be accessible independently of each other.
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Test Method for VLSI Semiconductor Chips
For testing a VLSI (very large-scale integration) semiconductor chip with
logic circuits and a storage embedded therein, the logic circuits and the storage
must be accessible independently of each other.
For this purpose, the conductors marked by broken lines in the figure are
additionally provided on the semiconductor chip. Also required are three control
signals for testing the logic circuits independently of the storage and for testing
the storage independently of the logic circuits. The first control signal,
designated as Degate Array Outputs (DAO), decouples the storage outputs from
the storage contents, thus causing these outputs to assume the high impedance
state. The second control signal, designated as Degate Array Inputs (DAI),
decouples the storage inputs from the logic controlling them, causing these
inputs to assume the high impedance state. The third signal, designated as
Degate Drivers (DDR), decouples the chip outputs from the control logic, causing
them to assume the high impedance state.
The control signals and the test pattern are supplied via the chip pads at
which also the test results may be received. Testing is effected as follows:
For testing the logic controlling the storage, control signals DAO and DDR
are applied, and the test pattern is fed to the chip inputs. The test results are
received at the chip outputs.
For testing the logic following the storage, control signals DAO and DAI are