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For keeping the area of semiconductor chips as small as possible, two-level decoding, instead of the usual one-level decoding, is used. Such two-level decoding is described in [*].
English (United States)
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High Speed Decoder Circuit with Low Power Requirements for Clock
Controlled Semiconductor Storages
For keeping the area of semiconductor chips as small as possible, two-level
decoding, instead of the usual one-level decoding, is used. Such two-level
decoding is described in [*].
In the case of the illustrated circuit arrangement, the charging of capacitance
CWBL on word-base line WBL at the beginning of the selection phase is avoided.
Capacitance CWBL is used to supply a high capacitive current pulse to the base
of the selected transistor TWL during switching, thus causing the potential of the
selected word line WL to be rapidly pulled down. For this purpose, the layout of
word line transistor TWL is chosen in such a manner that both the base-collector
and the base-emitter depletion layer capacitance are particularly high. The
operation of the circuit will be described below.
By switching off the transistor at the beginning of the standby phase, the
illustrated decoder circuit becomes almost currentless. Word-base line WBL and
thus capacitance CWBL are charged via resistor R1 until the base-collector path
of transistors TWL becomes conductive, thus maintaining the up-level of word-
base line WBL. As in the standby phase, each word line WL is connected to the
word reference line via saturated transistor TWR. The maximum level of the
word lines can rise only up to a voltage of 0.9 V + VCE-SAT (TWR) + VBC
(TWL)~/~1.6 V. As the internal voltage V+, to which resistor Rl is connected, is
only slightly above 1.6 V, the current flowing to the bases of transistors TWL
through resistor Rl is correspondingly low. The base current, however, is large
enough to inversely drive transistors TWL into saturation, so that the word-
emitter line is pulled down to the potential of word l...